Segmented digital-to-analog converter

ABSTRACT

In an embodiment, a digital-to-analog converter (DAC) converts an input digital signal into an output analog signal, and includes first and second segments, a combiner, and a controller. The first segment includes a first number of first elements that are configured to generate a first analog signal in response to a first portion of the digital signal, and the second segment includes a second number of second elements that are configured to generate a second analog signal in response to a second portion of the digital signal. The combiner is configured to combine the first analog signal and the second analog signal to generate the output analog signal, and the controller is configured to deactivate one of the first elements and to activate one of the second elements in place of the deactivated first element. For example, such a segmented DAC may be suitable for use in a sigma-delta ADC.

TECHNICAL FIELD

The present disclosure relates generally to electronic circuits andsignal processing, and more specifically to a segmenteddigital-to-analog converter (DAC), and to a sigma-deltaanalog-to-digital (ADC) converter that includes a segmented DAC in afeedback path of the ADC.

SUMMARY

In an embodiment, a segmented digital-to-analog converter (DAC) convertsan input digital signal into an output analog signal, and includes firstand second segments, a combiner, and a controller. The first segmentincludes a first number of first elements that are configured togenerate a first analog signal in response to a first portion of thedigital signal, and the second segment includes a second number ofsecond elements that are configured to generate a second analog signalin response to a second portion of the digital signal. The combiner isconfigured to combine the first analog signal and the second analogsignal to generate the output analog signal, and the controller isconfigured to deactivate at least one of the first elements and toactivate at least one of the second elements in place of the deactivatedat least one of the first elements.

For example, such a segmented digital-to-analog converter (DAC) may besuitable for use in a feedback path of a sigma-delta analog-to-digitalconverter (ADC). Such an ADC may have a signal-to-noise ratio (SNR) of100 decibels (dB) or higher, yet may have fewer components, and thus mayoccupy less area, than a conventional ADC having a comparable SNR.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a sigma-delta analog-to-digital converter (ADC)that includes a digital-to-analog converter (DAC) in a feedback path.

FIG. 2 is plot of the digital input versus the analog output of a linearDAC for two levels of output offset.

FIG. 3 is plot of the digital input versus the analog output of anon-linear DAC for two levels of output offset.

FIG. 4 is diagram of an unsegmented DAC.

FIG. 5 is a diagram of a segmented DAC.

FIG. 6 is a diagram of the operation of the segmented DAC of FIG. 5.

FIG. 7 is a diagram of a segmented DAC, according to an embodiment.

FIG. 8 is a diagram of the segments of a 5-bit version of the segmentedDAC of FIG. 7, according to an embodiment.

FIG. 9 is a diagram of the operation of the 5-bit version of thesegmented DAC of FIGS. 7-8, according to an embodiment.

FIG. 10 is a diagram of the segments of a 6-bit version of the segmentedDAC of FIG. 7, according to an embodiment.

FIGS. 11A-11D are diagrams of the operation of the 6-bit version of thesegmented DAC of FIGS. 7 and 10, according to an embodiment.

FIG. 12 is a diagram of a system including a sigma-delta ADC thatincorporates the segmented DAC of FIG. 7, according to an embodiment.

DETAILED DESCRIPTION

FIG. 1 is a diagram of a sigma-delta analog-to-digital converter (ADC)10.

In general, the sigma-delta ADC 10 oversamples an input analog signalANALOG_IN, and converts the oversampled analog signal ANALOG_IN into anoutput digital signal DIGITAL_OUT having a sample rate that is lowerthan the oversampling rate; for example, the sample rate may be at ornear the Nyquist frequency, and the oversampling rate may be 128 timesthe sample rate. The sigma-delta ADC 10 can have relatively lowcomplexity and cost, and can occupy a relatively small area, and yetprovide a digital output signal having a relatively high resolution(e.g., 16-24 bits), high signal-to-noise ratio (SNR), and highlinearity, as compared to other types of ADCs (e.g., flash, successiveapproximation) of comparable resolution.

The sigma-delta ADC 10 includes a sample-and-hold (SAH) circuit 12, acombiner (an adder in the described embodiment) 14, a loop filter 16, anN-bit quantizer (e.g., a flash ADC) 18, a filter and decimator 20, andan N-bit feedback DAC 22. And the loop filter 16 includes twointegrators 24 and 26, three amplifiers 28, 30, and 32 having respectivegains G1, G2, and G3, and a combiner (an adder in the describedembodiment) 34. Because the loop filter 16 includes two integrators 24and 26, the ADC 10 may be referred to as a second-order sigma-delta ADC.

Still referring to FIG. 1, the operation of the sigma-delta ADC 10 isdescribed.

The SAH circuit 12 oversamples the analog input signal ANALOG_IN at anoversampling rate that is significantly higher (e.g., 128 times higher)than the Nyquist frequency, which is twice ANALOG_IN'S highest frequencycomponent of interest.

During a sampling period, the SAH circuit 12 generates an analog sampleS of the input analog signal ANALOG_IN, and the combiner 14 subtractsfrom this analog sample S an analog feedback signal FEEDBACK to generatean analog difference, or error, signal E.

The filter 16 filters the analog difference signal E, and the quantizer18 converts the analog filtered signal AF into an intermediate digitalsignal ID having a resolution (e.g., 2-6 bits) that is significantlyless than the resolution (e.g., 16-24 bits) of the output digital signalDIGITAL_OUT. Because circuitry within filter 16 may exhibit significantnon-linear behavior at the upper and lower limits of its input range,the quantizer 18 may limit its output range to prevent such non-linearbehavior. For example, if the quantizer 18 is a 5-bit quantizer, theninstead of generating the signal ID over the full range of 0 to 31, itmay limit the range of ID to 4 to 29; similarly, if the quanitzer is a6-bit quantizer, then, instead of generating the signal ID over the fullrange of 0 to 63, it may limit the range of ID to 6 to 58.

The filter and decimator 20 decreases the sample rate, and increases theresolution, of the intermediate digital signal ID to generate thedigital output signal DIGITAL_OUT.

And the N-bit feedback DAC 22 converts the intermediate digital signalID into the analog feedback signal FEEDBACK, and provides FEEDBACK tothe combiner 14.

The SAH circuit 12, combiner 14, loop filter 16, N-bit quantizer 18,filter and decimator 20, and N-bit feedback DAC 22 repeat theabove-described operational sequence for each subsequent sample S of theinput analog signal ANALOG_IN.

Still referring to FIG. 1, alternate embodiments of the ADC 10 arecontemplated. For example, the loop filter 16 may have an architecturethat is different from that described.

A potential problem with the sigma-delta ADC 10 of FIG. 1 is that theoutput digital signal DIGITAL_OUT may have a signal-to-noise ratio (SNR)that is too low for some applications.

For example, if the DAC 22 is a 4-bit DAC, the OSR is 128, and therequired SNR of the ADC 10 is 100 dB, then the linearity of the DACneeds to be better than 1 part in 100000/128 because the DACnon-linearity directly adds with the ADC input signal ANALOG_IN.Achieving such a high level of linearity for a standard 4-bit DAC 22 maybe difficult, and would probably increase the cost and complexity of theDAC 22 significantly.

Consequently, to insure that the feedback DAC 22 is linear, thesigma-delta ADC 10 may include a 1-bit quantizer 18 and a 1-bit feedbackDAC 22 (i.e., N=1). It is known that a 1-bit DAC is inherently linear,and that a linear feedback DAC will not add non-linear distortion to theinput samples S, and, therefore, will not add non-linear distortion tothe ADC output signal DIGITAL_OUT.

But a potential problem with the ADC 10 including a 1-bit quantizer 18and a 1-bit feedback DAC 22 is that the power of the quantization noisemay be too high for some applications. Even though the filter anddecimator 20 may filter out the quantization noise per above, the powerthat the ADC 10 consumes to generate the quantization noise iseffectively wasted because it is removed from DIGITAL_OUT.

And another potential problem with the ADC 10 including a 1-bitquantizer 18 and a 1-bit feedback DAC 22 is that the stability marginfor the loop formed by the combiner 14, filter 16, quantizer 18, andfeedback DAC 22 may be too low for some applications.

To overcome the problems of the quantization-noise power being too highand the stability margin for the loop being too low, the sigma-delta ADC10 may include a multi-bit (e.g., 4≦N≦6) quantizer 18 and a multi-bit(e.g., 4≦N≦6) feedback DAC 22.

But unfortunately, a multi-bit DAC 22 may have a non-linear output, andtherefore, may add non-linear distortion to the input samples S and tothe ADC output signal DIGITAL_OUT. And such non-linear distortion may becharacterized as noise that reduces the SNR of DIGITAL_OUT.

FIG. 2 is a plot of analog output signals 40 and 42 generated byrespective linear versions of the DAC 22 of FIG. 1 in response to alinearly ramping digital input signal. The output signal 40 is generatedby a linear, multi-bit first version of the DAC 22 having zero outputoffset, and the output signal 42 is generated by a linear, multi-bitsecond version of the DAC having a non-zero output offset.

The analog output signal 40 is linear because the gain of the firstversion of the DAC 22 is constant regardless of the value of the digitalinput signal. For example, for an input value of 8, the analog outputsignal 40 has a value of 80 millivolts, for a gain of 80/8=10 mV/(leastsignificant-bit (LSB)). Similarly, for an input value of 12, the analogoutput signal 40 has a value of 120 mV, also for a gain of 120/12=10mV/LSB. The straight dashed line 44 through the same respective point ofeach step of the analog output signal 40 shows that the gain of thefirst version of the DAC 22 is a constant 10 mV/LSB for the entire rangeof digital input values.

Furthermore, the first version of the DAC 22 has a zero output offsetbecause the analog output signal 40 equals zero for an input value of 0.Or, stated differently, the first version of the DAC 22 has a zerooutput offset because the plot of the analog output signal 40 interceptsthe y-axis at y=0.

Still referring to FIG. 2, the analog output signal 42 generated by thesecond version of the DAC 22 is also linear for the reasons describedabove.

But the second version of the DAC 22 has a non-zero output offsetbecause the analog output signal 42 equals a non-zero value for an inputvalue of 0. Because the analog output signal 42 equals 40 mV for aninput value of 0, the output offset of the second version of the DAC 22is 40 mV. Or, stated differently, the second version of the DAC 22 has a40 mV output offset because the plot of the analog output signal 42intercepts the y-axis at y=40 mV.

Referring to FIGS. 1 and 2, it can be shown mathematically that as longas the DAC 22 of the ADC 10 generates the signal FEEDBACK having aconstant gain and offset, the DAC will not introduce any non-lineardistortion into the signals FEEDBACK or DIGITAL_OUT even if the DACoutput offset does not equal zero. And when the gain and offset of theDAC 22 are constant, the loop filter 16, or the filter and decimator 20,can compensate for the affect that the gain or offset may have on theoutput digital signal DIGITAL_OUT by effectively applying to DIGITAL_OUTa compensating gain or offset. For example, if the DAC 22 offset is 40mV, then the filter 16 or the filter and decimator 20 effectively canadd −40 mV to DIGITAL_OUT to cancel the offset. Or, if, for example, thegain of the feedback DAC 22 is five, then the filter 16 or the filterand decimator 20 effectively can attenuate DIGITAL_OUT by ⅕ cancel outthe gain of the feedback DAC.

FIG. 3 is a plot of analog output signals 50 and 52 generated byrespective non-linear versions of the DAC 22 of FIG. 1 in response to alinearly ramping digital input signal. The signal 50 is generated by anon-linear, multi-bit first version of the DAC 22 having zero outputoffset, and the signal 52 is generated by a non-linear, multi-bit secondversion of the DAC having a non-zero output offset.

The analog output signal 50 is non-linear because the gain of the firstnon-linear version of the DAC 22 varies depending on the value of thedigital input signal. For example, for an input value of 8, the analogoutput signal 50 has a value of 90 mV, for a gain of 90/8=11.25 mV/LSB.But for an input value of 12, the analog output signal 50 has a value of120 mV, for a gain of 120/12=10 mV/LSB. Another way to view thisnon-linear gain is to look at the change in the output signal 50 foreach LSB increment of the digital input signal. For example, for an LSBincrement of the input signal from 3 to 4, the output signal 50increases by 20 mV, which is equivalent to a gain of 20 mV/LSB. But foran LSB increment of the input signal from 9 to 10, the output signal 50increases by only 5 mV, which is equivalent to a gain of 5 mV/LSB, whichis only 25% of the gain for the LSB increment from 3 to 4. Also, anotherindication of the non-linearity of the DAC 22 is that no straight linecan be drawn through the same relative point of each step of the outputsignal 50.

Furthermore, the first version of the nonlinear DAC 22 has a zero outputoffset because the analog output signal 50 equals zero for an inputvalue of 0.

The analog output signal 52 generated by the second non-linear versionof the DAC 22 is also non-linear for the reasons described above.

But the second non-linear version of the DAC 22 has a non-zero outputoffset because the analog output signal 52 equals a non-zero value foran input value of 0. Because the analog output signal 52 equals 40 mVfor an input value of 0, the output offset of the second non-linearversion of the DAC 22 is 40 mV.

Referring to FIGS. 1 and 3, it can be shown mathematically that if theDAC 22 of the ADC 10 generates the signal FEEDBACK having a non-constantgain, i.e., in a non-linear manner, then the DAC will introducenon-linear distortion into the signals FEEDBACK and DIGITAL_OUTregardless of whether the DAC output offset equals 0.

Although this non-linear distortion can be characterized and treated asnoise, at least some of noise caused by non-linear distortion may be atfrequencies so close to the sample frequency of DIGITAL_OUT that it isimpractical to impossible for the loop filter 16 or the filter anddecimator 20 (FIG. 1) to block all of this noise without also blockingfrequencies of interest, i.e., frequencies that compose the usefulspectrum of DIGITAL_OUT. Another way to view the resultant noise ofnon-linear distortion caused by a non-linear feedback DAC 22 is that itmay cause the frequency band that the quantization noise occupies to beclose to, or actually to overlap, the frequency band of the of-interestcomponents of DIGITAL_OUT.

Referring to FIGS. 1-3, one may reduce or eliminate the non-lineardistortion introduced into DIGITAL_OUT by a multi-bit version of thefeedback DAC 22 by shaping the non-linear-distortion noise such that itcan be filtered out of DIGITAL_OUT, or such that it is transformed in amanner that does not distort DIGITAL_OUT.

As described below, if the feedback DAC 22 is a non-linear multi-bitthermometer-coded DAC, then a technique for reducing or eliminating thenon-linear distortion that the DAC introduces into DIGITAL_OUT isdynamic element matching (DEM) such as data-weighted averaging (DWA).

FIG. 4 is a diagram of a non-linear multi-bit version of the DAC 22 ofFIG. 1.

This version of the DAC 22 includes 2^(N)−1 current-source elements 60₁-60 ₂ ^(N) ⁻¹, where N is the number of bits of the digital signalinput to the DAC. In the example shown in FIG. 4 and described below,the DAC 22 is a 4-bit thermometer-coded DAC (N=4) having 15current-source elements 60 ₁-60 ₁₅. Consequently, the number ofcurrent-source elements 60 is one less than the total number 2^(N) ofpossible values that the digital input signal can assume (this isbecause for an input value of zero, no current-source elements need tobe activated). In this example, because the total number of possiblevalues that the N=4-bit digital input signal can assume is 2⁴=16, thenumber of current-source elements 60 is equal to 16−1=15.

Ideally, each current-source element 60 has a same gain G, and,therefore, generates a same current I, as the other current-sourceelements when activated. The currents I from all of the current-sourceelements 60 are summed at a node 62, and the resulting currentI_(analog-output) is the output of the DAC 22; if the DAC 22 outputs avoltage, then the current I_(analog-output) may be coupled to atemperature-compensated impedance (not shown in FIG. 4) to generate anoutput voltage V_(analog-output) (not shown in FIG. 4).

Table I shows one possible, intuitive correspondence between the valuesof the 4-bit digital input signal and the ones of the current-sourceelements 60 activated to generate I_(analog-out).

TABLE I 4-bit value of digital input signal Active current-sourceelements 60 0000 None 0001 60₁ 0010 60₁-60₂  0011 60₁-60₃  0100 60₁-60₄ 0101 60₁-60₅  0110 60₁-60₆  0111 60₁-60₇  1000 60₁-60₈  1001 60₁-60₉ 1010 60₁-60₁₀ 1011 60₁-60₁₁ 1100 60₁-60₁₂ 1101 60₁-60₁₃ 1110 60₁-60₁₄1111 60₁-60₁₅

Referring to FIGS. 1-2 and 4, if the 4-bit thermometer-coded DAC 22 ofFIG. 4 is ideal, i.e., the gain G, and thus the current I, are the samefor all current-source elements 60, then the DAC 22 is linear, and for alinearly ramped digital input signal, I_(analog-output) is linear likethe signals 40 and 42. Such an ideal DAC 22 may be said to have matchingcurrent-source elements, or, more succinctly, matching elements.

Unfortunately, a thermometer-encoded DAC is rarely, if ever, ideal. Thatis, the gain G of, and the current generated by, one current-sourceelement is typically different, even if only slightly, from the gain of,and the current generated by, at least one of the other current-sourceelements.

For example, referring to FIGS. 1 and 3-4, if the 4-bitthermometer-coded DAC 22 of FIG. 4 is non-ideal, i.e., thecurrent-source element 60 ₁ has a gain G₁ and generates a current I₁,the current-source element 60 ₂ has a gain G₂ and generates a currentI₂, the current-source element 60 ₃ has a gain G₃ and generates acurrent I₃, and so on, then the DAC 22 is non-linear, and for a linearlyramped digital input signal, I_(analog) _(—) _(output) is non-linearlike the signals 50 and 52. Such a non-ideal DAC 22 may be said to havemismatched current-source elements, or, more succinctly, mismatchedelements.

Referring to FIG. 4 and Table I, one can see, for example, that thecurrent-source element 60 ₁ is active for all values of the digitalinput signal other than 0, that the current-source element 60 ₂ isactive for all values of the digital input signal other than 0 and 1,and that the current-source element 60 ₁₅ is active for only a 1111binary value for the digital input signal.

Therefore, the component of the non-linearity introduced, for example,by the element 60 ₁ has a much higher frequency than the component ofthe non-linearity introduced, for example, by the element 60 ₁₅;consequently, although the components of the non-linearity introduced bythe lower-numbered elements 60 (e.g., 60 ₁, 60 ₂, and 60 ₃) may befiltered out, the components of the non-linearity introduced by thehigher-numbered elements 60 (e.g., 60 ₁₃, 60 ₁₄, and 60 ₁₅) may beimpractical or impossible to filter out due to their lower frequencies.

Still referring to FIGS. 1 and 4 and to Table I, data-weighted averaging(DWA), which is a subset of dynamic element matching (DEM), is atechnique for effectively reducing or eliminating the non-lineardistortion that a non-linear thermometer-coded DAC 22 introduces intoits output signal FEEDBACK, and into the ADC 10 output signalDIGITAL_OUT.

In general, the DAC 22 implements DWA by activating, on average, eachelement 60 of the DAC 22 the same number of times as each of the otherelements 60. That is, the DAC 22 effectively keeps track of how manytimes each of the elements 60 has been activated, and strives tomaintain this number the same, or close to the same, for all elements60. For example, the DAC 22 may keep a relative +/− count for eachelement 60. In a detailed example, the count for the element 60currently having the highest number of activations may be 0, and thecounts for the other elements 60 may be −1 and lower. The DAC 22activates the elements 60 in a sequence that maintains the counts forall of the elements 60 at or near 0. For example, if the input digitalsignal has a sequence of values 0001, 0001, 0001, then, instead ofactivating the element 60 ₁ (and deactivating the elements 60 ₂-60 ₁₅)for three consecutive sample times per Table 1, the DAC 22 maysequentially activate (and deactivate) the following elements: activate60 ₁ (deactivate 60 ₂-60 ₁₅), activate 60 ₂ (deactivate 60 ₁ and 60 ₃-60₁₅), and activate 60 ₃ (deactivate 60 ₁-60 ₂ and 60 ₄-60 ₁₅).

It can be shown mathematically that DWA significantly reduces the levelof non-linearity that the non-linear multi-bit thermometer-coded DAC 22introduces into FEEDBACK and DIGITAL_OUT, or altogether eliminates thisnon-linearity from FEEDBACK and DIGITAL_OUT.

Referring again to FIG. 1, DWA does this by shifting the frequencycomponents of the non-linearity of the DAC 22 far enough above thefrequency band of interest for DIGITAL_OUT such that the loop filter 16,or the filter and decimator 20, can filter out the non-linearityfrequency components.

Specifically, the loop filter 16 or the filter and decimator 20effectively averages the non-linearity introduced by the DAC 22 suchthat the non-linearity appears to introduce a constant error to thenormalized gain α of the ADC 10 according to the following equation:

$\begin{matrix}{\alpha = {1 + \frac{e_{1} + \ldots + e_{2^{N} - 1}}{2^{N} - 1}}} & (1)\end{matrix}$where

$\frac{e_{1} + \ldots + e_{2^{N} - 1}}{2^{N} - 1}$is the error term, and e_(x), which can be positive or negative, is thedifference between the ideal gain G and the actual gain G_(x) of anelement 60 _(x).

But as described above, because the resulting gain kα (k is a scalarthat, when multiplied by the normalized gain α, yields the actual gain)of the DAC 22 is constant, the DAC 22 adds little or no non-linearity toits output signal FEEDBACK or to the ADC 10 output signal DIGITAL_OUT.

Consequently, referring to FIGS. 1-4, if one includes in the ADC 10 anon-linear thermometer-coded multi-bit DAC 22 that implements DWA, thenhe/she can realize the benefits (e.g., lower quantization-noise power,greater loop-stability margin) of a multi-bit quantizer 18 withoutintroducing significant non-linear distortion into the DAC output signalFEEDBACK or into the ADC output signal DIGITAL_OUT. For example, it canbe shown mathematically that if the maximum mismatch of the elements 60is ±5% (i.e., the difference between G_(x) for an element 60 _(x) andthe ideal gain G is no greater than the ±5%), then the ADC 10 cangenerate DIGITAL_OUT with an SNR of at least 120 dB if the DAC 22 is anon-linear, thermometer-coded, DWA DAC.

Referring to FIG. 4, alternate embodiments of the 4-bit DAC 22 arecontemplated. For example, the DAC current-source elements 60 may bereplaced with capacitive or other types of DAC elements.

Still referring to FIG. 4, a potential problem with even a DWA versionof the DAC 22 is that the number of DAC elements 60, and thus the numberof lines that carry the currents generated by the elements 60, increaseexponentially with the resolution of the quantizer 18. For example, theDWA version of the 4-bit DAC 22 of FIG. 4 has 15 lines and 15 DACelements 60, and a 5-bit DWA DAC would have 31 lines and 31 DACelements. But a 6-bit DWA DAC would have 63 lines and 63 DAC elements60, an 8-bit DWA DAC would have 255 lines and 255 DAC elements, and a16-bit DWA DAC would have 65,535 lines and 65,535 DAC elements!

FIG. 5 is a diagram of a segmented 5-bit DAC 70, according to anembodiment. As described below, segmenting a DAC allows one to increasethe resolution of the quantizer 18 of the ADC 10 of FIG. 1 withoutexponentially increasing the number of DAC elements and element lines.

Referring to FIG. 5, the 5-bit DAC 70 has a first, 4-bit segment 72, andhas a second, 1-bit segment 74.

The first segment 72, which may be similar to the DWA version of the DAC22 of FIG. 4, provides the components of I_(analog) _(—) _(output)corresponding to the four most-significant bits (MSBs) of the digitalinput signal, includes fifteen DAC current-source elements 76 ₁-76 ₁₅each having a gain of approximately 2G, and implements DWA as describedabove in conjunction with FIG. 4.

The second segment 74 provides the component of I_(analog) _(—) _(out)corresponding to the least-significant bit (LSB) of the digital inputsignal, and includes a single DAC current element 78 ₁ having a gain ofapproximately G, which, is ½ of the ideal gain 2G of each of the currentelements 76 of the first segment 72. The reason for this gain scalingbetween the first and second segments 72 and 74 is that the component ofI_(analog) _(—) _(out) provided by the element 78 ₁ corresponds to the2° bit position of the digital input signal, and the components ofI_(analog-out) respectively provided by the elements 76 each correspondto the 2¹ bit position of the digital input signal.

FIG. 6 is a flow diagram of the operation of the segmented DAC 70 ofFIG. 5.

Referring to FIGS. 5-6, operation of the DAC 70 is described.

At a step 80, a controller or other circuit (not shown in FIG. 5)divides the digital input value x by 2 (x/2 or x modulo 2) to generate a4-bit quotient q and a 1-bit remainder r.

At steps 82 and 84, the DWA first segment 72 generates a first componentI_(component) _(—) ₁ of I_(analog) _(—) _(output) in response to q andindependently of r.

At step 82, the first segment 72 first determines how many of thecurrent elements 76 are to be activated in response to q. For example,if q=0101, then the first segment 72 determines that five of the currentelements 76 are to be activated, and if q=1000, then the first segmentdetermines that eight of the current elements 76 are to be activated.Next, the first segment 72 uses DWA to determine which of the currentelements 76 to activate, and activates these current elements.

At step 84, the DWA first segment 72 multiplies by two the currentresulting from the activated current elements 76. In actuality, becausethe ideal gains of the current elements 76 are twice the ideal gain ofthe element 78, the current elements 76 inherently perform thismultiplication by two.

And, at step 86, the second segment 74 generates a second componentI_(component) _(—) ₂ of I_(analog-output) in response to r andindependently of q. For example, if r=0, then the second segment 74 doesnot activate the current element 78, and if r=1, then the second segmentactivates the current element 78; that is, for even values of x, r=0 andthe element 78 is inactive, and for odd values of x, r=1 and the element78 is active.

And, at a step 88, the components I_(component) _(—) ₁ and I_(component)_(—) ₂ from the first and second segments 72 and 74 are summed togenerate I_(analog) _(—) _(out).

Still referring to FIGS. 5 and 6, alternate embodiments of the DAC 70are contemplated. For example, the DAC 70 may have more than twosegments, and the current-source elements 76 may be replaced withcapacitor or other types of DAC elements. Furthermore, the stepsdescribed in conjunction with FIG. 6 may be performed in any othersequence or during overlapping time periods, and some steps may beomitted and other steps may be added, depending on the application inwhich the DAC 70 is used.

Referring to FIGS. 1 and 5-6, a potential problem with the DAC 70 isthat if it is used in the ADC 10 as the feedback DAC 22, then, the SNRsof FEEDBACK DIGITAL_OUT are significantly degraded even though the firstDAC segment 72 operates according to a DWA algorithm. For example, evenwith a maximum mismatch between the current-source elements 76 and 78 of±1%, the SNR of DIGITAL_OUT is less than 90 dB, which may be too low forsome applications.

One reason for the degraded SNRs is that due to mismatches between thecurrent-source element 78 and the current-source elements 76, the gainsof the first and second DAC segments 72 and 74 will typically bedifferent, and this gain difference will not be constant, but willdepend on the value of the input digital signal x; it is this gaindifference that gives rise to a SNR-reducing non-linearity of thesignals FEEDBACK and DIGITAL_OUT of the ADC 10 (FIG. 1).

And, unfortunately, DWA is not a solution to this potential problem.Because the current-source element 78 of the DAC 70 has a differentgain, i.e., weight, than the current-source elements 76, one cannotextend the DWA operation of the first segment 72 to the second segment74; that is, the DAC 70 cannot swap the element 78 with any of theelements 76 without causing significant error in I_(analog) _(—) _(out)(FEEDBACK) and in DIGITAL_OUT.

FIG. 7 is a diagram of an N-bit segmented DAC 90, which, when used inthe ADC 10 of FIG. 1, can allow the feedback signal FEEDBACK and the ADCoutput signal DIGITAL_OUT to have a higher SNRs as compared to thesegmented DAC 70 of FIG. 5. For example, with a maximum, random mismatchof ±1% for the DAC elements in the different segments of the DAC 90, theSNR of DIGITAL_OUT may be 100 dB or greater, such as 120 dB or greater.

The N-bit segmented DAC 90 includes an input-value divider 92, an m-bitfirst segment 94, a p-bit second segment 96, a combiner 100, and acontroller 102. The DAC 90 outputs an analog signal ANALOG_OUT, whichmay be a current I_(analog) _(—) _(out) or a voltage V_(analog) _(—)_(out).

During operation of the DAC 90, the controller 102 causes the divider92, first segment 94, second segment 96, and combiner 100 to operate asfollows.

First, the divider 92 divides the digital input value x by 2^(p)(x/2^(p) or x modulo 2^(p)) to generate an m-bit quotient q and a p-bitremainder r. In an example, N=5, m=4, p=1, and 2P=2¹=2.

Next, the m-bit first segment 94 generates a first component COMPONENT_1of the DAC output signal ANALOG_OUT in response to q and r. First, thecontroller 102 determines, in response to q and the value and cycleposition of r, if any of the DAC elements of the second segment 96 areto be swapped for any of the DAC elements of the first segment 94. Forexample, if p=1, r has two possible values, 0 and 1. If two occurrencesof r=0 form a sequence, or cycle, of 0s, then the first occurrence ofr=0 in a cycle of 0s is in a first cycle position, and the secondoccurrence of r=0 in a cycle of 0s is in a second cycle position. If thecontroller 102 determines that at least one of the DAC elements of thesecond segment 96 is to be swapped for at least one of the DAC elementsof the first segment 94, then the controller 102 generates acorresponding value y≠0; if not, the controller generates y=0. Then, thecontroller 102 determines a number of DAC elements of the first segmentto be activated in response to q−y. For example, if m=4 and q−y=0101,then the first segment 94 determines that five of its DAC elements areto be activated, and if q−y=1000, then the controller 102 determinesthat eight of its DAC elements are to be activated. Next, the controller102 operates according to a DWA algorithm to select which of its DACelements to activate; that is, continuing the above example, ifq−y=0101, then the controller uses DWA to select the five DAC elementsof the first segment 94 to activate, and if q−y=1000, then thecontroller uses DWA to select the eight DAC elements of the first DACsegment to activate. Then, the controller 102 activates the selected DACelements of the first DAC segment 94. The operation of the first DACsegment 94 is described in more detail below in conjunction with FIGS.8-11.

Then, the second DAC segment 96 of the DAC 90 generates a secondcomponent COMPONENT_2 of ANALOG_OUT in response to the current value ofr, the cycle position associated with the current value of r, andpossibly q (for example, the second DAC segment may be responsive to qwhen x=q=r=0 so that no DAC elements of the first and second DACsegments are activated when the input digital signal is zero). Theoperation of the second DAC segment 96 may overlap in time theabove-described operation of the first DAC segment 94.

Next the combiner 100 adds together the components COMPONENT_1 andCOMPONENT_2 from the first and second DAC segments 94 and 96 to generatethe analog output signal ANALOG_OUT of the DAC 90.

Still referring to FIG. 7, alternate embodiments of the segmented DAC 90are contemplated. For example, the DAC 90 may include more than twosegments 94 and 96. Furthermore, the combiner 100 may perform acombining operation other than adding.

FIG. 8 is a diagram of the first and second segments 94 and 96 and thecombiner 100 of a 5-bit current-output version of the DAC 90 of FIG. 7,according to an embodiment where N=5, m=4, and p=1.

The 4-bit first segment 94, which may be similar to the 4-bit segment 72of the DAC 70 of FIG. 5, is configured to generate a first component ofI_(analog) _(—) _(out) corresponding to the four most-significant bits(MSBs) of the digital input signal x, and includes fifteen DACcurrent-source elements 104 ₁-104 ₁₅ each having a gain of approximately2G, which is the ideal gain for each of the current-source elements 104.Specifically, each element 104 _(x) has a gain of 2G+e_(x), where e_(x)is the gain error having a positive or negative value. For example,e_(x) may be approximately in the range of 0%-5% of 2G.

The second segment 96 is configured to generate a second component ofI_(analog) _(—) _(out) corresponding to the least-significant bit (LSB)of the digital input signal x, and includes two DAC current-sourceelements 106 ₁-106 ₂ each having a gain of approximately G, which is theideal gain for each of the current-source elements 104, and which is ½of the ideal gain 2G of each of the current elements 104 of the firstsegment 94. Specifically, each current element 106 _(x) has a gain ofG+e_(x), where e_(x) is the gain error having a positive or negativevalue. For example, e_(x) may be in the range of 0%-5% of G. The reasonfor this gain scaling of two between the first and second segments 94and 96 is that the component of I_(analog) _(—) _(out) generated by theelements 106 ₁-106 ₂ corresponds to the 2⁰ bit position of digital inputsignal x, and the component of I_(analog-out) generated by the elements104 corresponds the 2¹ bit position of x.

And the combiner 100 is a current-summing node to which the outputs ofall of the current elements 104 and 106 are coupled.

Even though the 5-bit segmented DAC 90 of FIG. 8 includes one additionalcurrent element 106 ₂ (for a total of 17 elements 104 and 106 and 17lines respectively coupled to these elements) as compared to the 5-bitsegmented DAC 70 of FIG. 5, this is still significantly fewer DACelements and lines than a 5-bit DWA DAC, which includes 31 DAC elementsand 31 lines.

In general, as described in more detail below, an embodiment of the5-bit version of the DAC 90 generates I_(analog) _(—) _(out) with lessnon-linear distortion than the segmented DAC 70 of FIG. 5 by sometimesswapping both of the current elements 106 of the second segment 96 forone of the current elements 104 of the first segment 94. The controller102 (FIG. 7) operates the 4-bit first DAC segment 94 in a DWA fashion,except that sometimes, instead of activating all of the current elements104 needed to generate the first component of I_(analog) _(—) _(out),the controller deactivates, or maintains inactive, one of these currentelements 104, and, in its place, activates both of the current elements106.

Still referring to FIG. 8, Table I describes the activation of the DACelements 106 of the second DAC segment 96 versus the current value andcycle position of the remainder r, according to an embodiment.

TABLE I r cycle DAC element DAC element q r position 106₂ 106₁  0 0Don't care Inactive Inactive ≠0 0 1^(st) position Inactive Inactive ≠0 02^(nd) position Active and Active and swapped swapped Don't care 11^(st) position Inactive Active and not swapped Don't care 1 2^(nd)position Active and not Inactive swapped

One can make the following observations from Table I. When q=0 and r=0,which means that x=0, then the DAC elements 104 and 106 are allinactive, and, therefore, no swapping occurs. When q≠0 and r=0, in thefirst cycle position the DAC elements 106 ₁ and 106 ₂ are both inactive,and, therefore, no swapping occurs; but in the second sequence position,the DAC elements 106 ₁ and 106 ₂ are both active, and the controller 102(FIG. 7) deactivates, or maintains inactive, one of the DAC elements 104such that the active elements 106 ₁ and 106 ₂ are effectively swappedfor the inactive DAC element 104 that would otherwise be active. Thecontroller 102 activates two current elements 106 as a replacement forone current element 104 because the gains of the current elements 106are each approximately ½ of the gains of the current elements 104. Andwhen r=1, regardless of the value of q, in the first cycle positionelement 106 ₁ is active and element 106 ₂ is inactive because only oneof the elements 106 need be active in response to the LSB of x equaling1, and in the second cycle position the element 106 ₁ is inactive andthe element 106 ₂ is active.

Still referring to Table I, in summary, by alternately swapping theelements 106 for an element 104 in response to r=0 (and q≠0), and byalternately activating the elements 106 ₁ and 106 ₂ in response to r=1,the controller 102 operates the first and second DAC segments 94 and 96in a manner that shapes the non-linearity noise caused by the gaindifference between the first and second DAC segments. Specifically, thecontroller 102 effectively pushes this non-linearity noise to higherfrequencies so that more of this noise can be removed by the filter 16,or by the filter and decimator 20, of FIG. 1 as compared to thesegmented DAC 70 of FIG. 5.

FIG. 9 is a flow diagram of the operation of the 5-bit version of thesegmented DAC 90 of FIGS. 7 and 8, according to an embodiment.

Referring to FIGS. 7-9, the operation of the DAC 90 is described,according to an embodiment.

At step 110, the controller 102 divides the digital input value x by2^(P)=2¹=2 to generate a 4-bit quotient q and a 1-bit remainder r.

During a first cycle position for r=0, at step 112 the controller 102deactivates the second DAC segment 96 (DAC2 in FIG. 9).

At step 114, the controller 102 determines how many of thecurrent-source elements 104 of the first DAC segment 94 (DAC1 in FIG. 9)are to be activated in response to q (the value y described above inconjunction with FIG. 7 is 0), determines which of the elements toactivate using DWA, and then activates these elements. For example, ifq=0101, then the controller 102 determines that five of the currentelements 104 are to be activated, uses DWA to determine which five ofthe current elements 104 to activate, and activates these five currentelements 104.

Then, at step 116, the first DAC segment 94 effectively multiplies byapproximately two the signal generated by the active elements 104 togenerate I_(analog) _(—) _(output) (because the second DAC segment 96 isinactive, the first DAC segment generates I_(analog) _(—) _(out) in itsentirety). As described above, this multiply by two is because theelements 104 each correspond to a bit in the 2¹=2 bit position of x, andis inherently effected by the gain of each of the DAC elements 104 ofthe first DAC segment 94 being approximately twice the gain of each ofthe DAC elements 106 of the second DAC segment 96.

During a second cycle position for r=0, at step 117 the controller 102activates the elements 106 ₁ and 106 ₂ of the second DAC segment 96(DAC2 in FIG. 9) to generate a second component of I_(analog-out)—asdescribed above, however, the controller 102 deactivates the elements106 ₁ and 106 ₂ if q=x=r=0.

At step 118, the controller 102 subtracts y=1 one from q because theactive elements 106 ₁ and 106 ₂ take the place of one of the currentelements 104 that the controller would otherwise activate in response toq.

Then, at step 120, the controller 102 determines how many of the currentelements 104 of the first DAC segment 94 (DAC1 in FIG. 9) are to beactivated in response to q−1, determines which of the elements toactivate using DWA, and then activates these elements. For example, ifq=0101, then q−0001=0100 and the controller 102 determines that four ofthe current elements 104 are to be activated. Next, the controller 102uses DWA to determine which of the four current elements 106 toactivate, and activates these four current elements.

Next, at step 122, the first DAC segment 94 effectively multiplies byapproximately two the signal generated by the active elements 104 togenerate a first component of I_(analog) _(—) _(output). As describedabove, this multiply by two is because the elements 104 each correspondto a bit in the 2¹=2 bit position, and is inherently effected by thegain of each of the DAC elements 104 of the first DAC segment 94 beingapproximately twice the gain of each of the DAC elements 106 of thesecond DAC segment 96.

Then, at step 124, the first and second components of I_(analog) _(—)_(out) are summed at the summing node 100 to generate I_(analog) _(—)_(out).

The controller 102 keeps track of the cycle positions for r, and repeatsthe above-described sequential, cyclic, procedure for subsequentoccurrences of r=0.

Still referring to FIG. 9, during a first cycle position for r=1, atstep 126 the controller 102 activates the element 106 ₁ and deactivatesthe element 106 ₂ of the second DAC segment 96 (DAC2 in FIG. 9) togenerate a second component of I_(analog-out).

At step 128, the controller 102 determines how many of the currentelements 104 of the first DAC segment 94 (DAC1 in FIG. 9) are to beactivated in response to q (y=0 because this is the first cycle positionof r=1), determines which of the elements to activate using DWA, andthen activates these elements. For example, if q=0101, then thecontroller 102 determines that five of the current elements 104 are tobe activated. Next, the controller 102 uses DWA to determine which fiveof the current elements 104 to activate, and activates these fivecurrent elements.

Then, at step 130, the first DAC segment 94 effectively multiplies byapproximately two the signal generated by the active elements 104 togenerate a first component of I_(analog) _(—) _(output). As describedabove, this multiply by two is because the elements 104 each correspondto a bit in the 2¹=2 bit position, and is inherently effected by thegain of each of the DAC elements 104 of the first DAC segment 94 beingapproximately twice the gain of each of the DAC elements 106 of thesecond DAC segment 96.

Next, at step 132, the first and second components of I_(analog) _(—)_(out) are summed at the summing node 100 to generate I_(analog) _(—)_(out).

And during a second cycle position for r=1, at step 134 the controller102 deactivates the element 106 ₁ and activates the element 106 ₂ of thesecond DAC segment 96 (DAC2 in FIG. 9) to generate a second component ofI_(analog-out).

At step 136, the controller 102 determines how many of the currentelements 104 of the first DAC segment 94 (DAC1 in FIG. 9) are to beactivated in response to q (y=0 because this is the first cycle positionof r=1), determines which of the elements to activate using DWA, andthen activates these elements. For example, if q=0101, then thecontroller 102 determines that five of the current elements 104 are tobe activated. Next, the controller 102 uses DWA to determine which fiveof the elements 104 to activate, and activates these five elements.

Then, at step 138, the first DAC segment 94 effectively multiplies byapproximately two the signal generated by the active elements 104 togenerate a first component of I_(analog) _(—) _(output). As describedabove, this multiply by two is because the elements 104 each correspondto a bit in the 2¹=2 bit position, and is inherently effected by thegains of each of the DAC elements 104 of the first DAC segment 94 beingapproximately twice the gain of each of the DAC elements 106 of thesecond DAC segment 96.

Next, at step 140, the first and second components of I_(analog) _(—)_(out) are summed at the summing node 100 to generate I_(analog) _(—)_(out).

The controller 102 keeps track of the cycle positions for r, and repeatsthe above-described sequential, cyclic procedure for subsequentoccurrences of r=1.

Still referring to FIGS. 7-9, as described above, the first DAC segment94 uses DWA to average/remove the non-linearity caused by its mismatcherror by converting the mismatch error to a constant gain error, atleast ideally.

For the second DAC segment 96, the average mismatch error over afour-cycle grouping of the possible two even events (r=0) and the twopossible odd events (r=1) is a constant output offset β given by thefollowing equation:

$\begin{matrix}{\beta = \frac{e_{106\_ 1} + e_{106\_ 2}}{2}} & (2)\end{matrix}$where e₁₀₆ _(—) ₁=G₁₀₆ _(—) ₁−G is the quantization error of the element106 ₁, and e₁₀₆ _(—) ₂=G₁₀₆ _(—) ₂−G is the quantization error of theelement 106 ₂, such that the mismatch error of the second DAC segment 96is effectively converted into the constant offset error β (as describedabove e₁₀₆ _(—) ₁ and e₁₀₆ _(—) ₂ can be positive or negative).

As described above, because the mismatch errors of the first and secondDAC segments 94 and 96 are, at least ideally, converted into a constantgain error and a constant offset error β, respectively, the mismatcherror introduced by component mismatch in the first and second DACsegments is effectively eliminated, and, therefore, adds no nonlinearitynoise that degrades the SNR of the segmented DAC 90, or of a sigma-deltaADC that incorporates the segmented DAC.

But because the DAC elements 106 ₁ and 106 ₂ of the second DAC segment96 are sometimes “swapped” into the first DAC segment 94 as describedabove to obtain the constant offset β for the second DAC segment, theeffective gain error of the first DAC segment is, in actuality, notconstant, and, therefore, this non-constant gain error does add somenon-linearity noise that does degrade the SNR of the 5-bit version ofthe segmented DAC 90. Specifically, the normalized gain α of the firstDAC segment 94 is given by the following equation:

$\begin{matrix}{\alpha = {1 + \frac{e_{104\_ 1} + \ldots + e_{104\_ 15}}{den}}} & (3)\end{matrix}$where the rightmost term of the right side of equation (3) is the gainerror, and den (short for “denominator”) has a variation depending uponthe sequence of input numbers from the quantizer 18 (FIG. 1) to the5-bit version of the segmented feedback DAC 90. For example, if thesequence from the quantizer 18 is of all similar numbers, for example,4, 4, 4, . . . 4, or 7, 7, 7, . . . , 7, then den is given by thefollowing equation:

$\begin{matrix}{{den} = {\left\{ {x*\frac{15}{{quotient}\left( \frac{x}{2} \right)}*{{remainder}\left( \frac{x}{2} \right)}} \right\} + \left\{ {x*\frac{15}{{{quotient}\left( \frac{x}{2} \right)} - \frac{1}{2}}*{{{{remainder}\left( \frac{x}{2} \right)} - 1}}} \right\}}} & (4)\end{matrix}$where, for example, quotient (5/2)=2 and remainder (5/2)=1.

The range of the gain α for any sequence of numbers from the quantizer18 (FIG. 1) is as follows:

$\begin{matrix}{\alpha = {{1 + {\frac{e_{104\_ 1} + \ldots + e_{104\_ 15}}{60}\mspace{14mu}{to}\mspace{14mu}\alpha}} = {1 + \frac{e_{104\_ 1} + \ldots + e_{104\_ 15}}{31}}}} & (5)\end{matrix}$(i.e., 31≦den≦60, where den may take on a non-integer value within thisrange).

Furthermore, per equation (2), the offset error for the 5-bit version ofthe segmented DAC 90 is

${\beta = \frac{e_{106\_ 1} + e_{106\_ 2}}{2}},$which is constant for any sequence whatsoever; the offset β includesnonzero terms only from the mismatch errors of the elements of thesecond DAC segment 96.

If there is a sufficiently “busy” input signal to the sigma-delta ADC 10(FIG. 1), the output of the quantizer 18 (FIG. 1) varies significantlysuch as in the sequence (4, 5, 6, . . . , 29, 4, 5, 6, . . . , 29, . . .). For such a quantizer sequence, the gain α of the first segment 94 ofthe 5-bit version of the DAC 90, when the DAC 90 is used as the feedbackDAC 22 of the ADC 10 of FIG. 1, is, or is close to:

$\begin{matrix}{\alpha = {1 + \frac{e_{104\_ 1} + \ldots + e_{104\_ 15}}{31}}} & (6)\end{matrix}$

That is, den is, or is close to, 31, which is at the lower end of theden range, thus allowing the gain α to approach the gain of a 5-bit DWADAC per equation (1) above. Or, viewed another way, for a “busy”quantizer sequence, the gain error (the rightmost term of the right sideof equation (6)) of the first segment 94 of the 5-bit version of thesegmented DAC 90 approaches the gain error of a 5-bit non-segmented DWADAC.

If there is a mismatch error of no more than 1% (i.e., G₁₀₄ _(—)_(x)−G≦±0.01·G and G₁₀₆ _(—) _(x)−2G≦±0.01·2G) with the elements 104 and106 of the first and second DAC segments 94 and 96, then, as describedabove, the variation of the first-segment gain α, and, therefore, thevariation in the linear distortion in the output of the 5-bit segmentedDAC 90, will depend upon the sequence of values input to the DAC. Butextensive MATLAB simulations have shown that for a mismatch error of notmore than 1%, the SNR of the ADC 10 (FIG. 1), when incorporating the DAC90 as the feedback DAC 22, remains better than 120 dB. This implies thatthe variation in the gain error (the right-most term on the right sideof equation (6) above) is below −120 dB.

Furthermore, if the gain α of the first segment 94 of the 5-bit versionof the DAC 90 varies from α₁ to α₂, then the noise introduced into theoutput ANALOG_OUT of the ADC 10 (FIG. 1) by the feedback DAC is given bythe following equation:

$\begin{matrix}{20*\log\; 10\left\{ \frac{\alpha_{1} - \alpha_{2}}{{oversampling}\mspace{14mu}{rate}} \right\}} & (7)\end{matrix}$

If the gain α varies between more than two values, then the expressionfor the introduced noise may be more complex, but the SNR of ANALOG_OUTwill still remain better than 120 dB for the ADC 10 using, as thefeedback DAC 22, the 5-bit version of the segmented DAC 90 at anoversampling rate of at least 128.

Referring to FIGS. 7-8, alternate embodiments of the 5-bit version ofthe segmented DAC 90 are contemplated. For example, instead of the DACcurrent-source elements 104 and 106, the first and second DAC segments94 and 96 may include capacitor elements or other types of DAC elements.

FIG. 10 is a diagram of the first and second DAC segments 94 and 96 andthe combiner 100 of a 6-bit current-output version of the DAC 90 of FIG.7, according to an embodiment where N=6, m=4, and p=2.

The 4-bit first segment 94, which may be similar to the 4-bit firstsegment 94 of the 5-bit version of the DAC 90 of FIG. 7, provides thecomponent of I_(analog) _(—) _(out) corresponding to the four MSBs ofthe digital input signal x, and includes fifteen DAC current-sourceelements 150 ₁-150 ₁₅ each having a gain of approximately 4G, which isthe ideal gain of each element 150. Specifically, each current element150, has a gain of 4G+e_(x), where e_(x) is the gain error and may be apositive or negative value. For example, e_(x) may be in the range of0%-±5% of 4G.

The second segment 96 provides the component of I_(analog) _(—) _(out)corresponding to the two LSBs of the digital input signal x, andincludes four DAC current-source elements 152 ₁-152 ₄. Thecurrent-source elements 152 ₁-152 ₂ have a gain of approximately G,which is the ideal gain of these elements and which is ¼ of the idealgain 4G of each of the current elements 150 of the first segment 94.Specifically, each element 152 ₁-152 ₂ has a gain of G+e_(x), wheree_(x) is the gain error and may be a positive or negative value. Forexample, e_(x) may be in the range of 0%-±5% of G. And the currentelements 152 ₃-152 ₄ each have a gain of approximately 2G, which is theideal gain of these elements and which is ½ of the ideal gain 4G of eachof the current elements 150 of the first segment 94. Specifically, eachcurrent element 152 ₃-152 ₄ has a gain of 2G+e_(x), where e_(x) is thegain error and may be a positive or negative value. For example, e_(x)may be in the range of 0%-±5% of 2G. The reason for this gain scalingbetween the first and second segments 94 and 96 is that the component ofI_(analog) _(—) _(out) provided by the elements 152 ₁-152 ₄ correspondsto the 2⁰ and 2¹ bit positions of the value x of the digital inputsignal, and the components of I_(analog-out) respectively provided bythe elements 150 correspond to the 2² bit position of x.

And the combiner 100 is a current-summing node to which the outputs ofall of the current elements 150 and 152 are coupled.

Even though the 6-bit version of the segmented DAC 90 of FIGS. 7 and 10includes two additional current elements 152 ₄, 152 ₃, and 152 ₂ (for atotal of 19 elements 150 and 152 and 19 lines that carry the currentsgenerated by these elements) as compared to a standard 6-bit segmentedDAC, which would have 17 DAC elements and lines, this is stillsignificantly fewer than the 63 DAC elements that a 6-bit DWA DACincludes.

In general, as described in more detail below, the 6-bit version of theDAC 90 generates I_(analog) _(—) _(out) with less non-linear distortionthan a 6-bit version of the segmented DAC 70 of FIG. 5 by sometimesswapping two, three, or four of the current-source elements 152 of thesecond segment 96 for one of the current-source elements 150 of thefirst segment 94. The controller 102 (FIG. 7) operates the 4-bit firstDAC segment 94 in a DWA fashion, but sometimes, instead of activatingall of the elements 150 needed to generate the first component ofI_(analog) _(—) _(out) in response to q, the controller deactivates, ormaintains inactive, one of these elements 150, and, in its place,activates at least one (e.g., two or three) of the current elements 152.

Table II describes the activation of the DAC elements 152 of the secondDAC segment 96 of FIG. 10 versus the present value and cycle position ofr, according to an embodiment.

TABLE II DAC DAC DAC DAC r cycle element element element element q rposition 152₄ 152₃ 152₂ 152₁  0 0 Don't care Inactive Inactive InactiveInactive ≠0 0 1^(st) position Inactive Inactive Inactive Inactive ≠0 02^(nd) Inactive Active and Active and Active and position SwappedSwapped Swapped ≠0 0 3^(rd) Active and Inactive Active and Active andposition Swapped Swapped Swapped ≠0 0 4^(th) Active and Active andInactive Inactive position Swapped Swapped ≠0 1 1^(st) position InactiveInactive Inactive Active But not swapped ≠0 1 2^(nd) Inactive InactiveActive But Inactive position not swapped ≠0 1 3^(rd) Active and Activeand Inactive Active But position Swapped Swapped Not Swapped ≠0 1 4^(th)Active and Active and Active But Inactive position Swapped Swapped NotSwapped ≠0 2 1^(st) Inactive Inactive Active But Active But position notnot swapped swapped ≠0 2 2^(nd) Inactive Active But Inactive Inactiveposition not swapped ≠0 2 3^(rd) Active But Inactive Inactive Inactiveposition not swapped ≠0 2 4^(th) Active and Active and Active But ActiveBut position swapped swapped not not swapped swapped ≠0 3 1^(st)Inactive Active But Inactive Active But position not not swapped swapped≠0 3 2^(nd) Active But Inactive Inactive Active But position not notswapped swapped ≠0 3 3^(rd) Inactive Active But Active But Inactiveposition not not swapped swapped ≠0 3 4^(th) Active But Inactive ActiveBut Inactive position not not swapped swapped

One can make the following observations from Table II. When x=q=r=0,then the DAC elements 150 and 152 are all inactive, and, therefore, noswapping occurs regardless of the cycle position of r. Furthermore,because the gain of each element 150 is approximately two times the gainof each element 152 ₃ and 152 ₄, and is approximately four times thegain of each element 152 ₁ and 152 ₂, the only combinations of theelements 152 that can be swapped into the first DAC segment 94 are: 152₃ and 152 ₄; 152 ₁, 152 ₂, and 152 ₃; and 152 ₁, 152 ₂, and 152 ₄.

Still referring to Table II, in summary, by alternately swapping theelements 152 for an element 150, and by alternately activating theelements 152 ₁, 152 ₂, 152 ₃, and 152 ₄, the controller 102 operates thefirst DAC segment 94 in a DWA fashion, and operates the second DACsegment 96 in a manner that pushes the non-linearity noise caused by theelement mismatches in, and the gain differences between, the DACsegments 94 and 96 to higher frequencies so that more of this noise canbe removed by the filter and decimator 20 of FIG. 1 as compared to thesegmented DAC 70 of FIG. 5.

FIGS. 11A-11D are flow diagrams of the operation of the 6-bit version ofthe segmented DAC 90 of FIGS. 7 and 10, according to an embodiment.

Referring to FIGS. 7, 10, and 11A-11D, the operation of the 6-bitversion of the DAC 90 is described, according to an embodiment.

At a step 160, the controller 102 divides the digital input value x by2^(P)=2²=4 to generate a 4-bit quotient q and a 2-bit remainder r.

During a first sequence, or cycle, position for r=0, at step 162 thecontroller 102 deactivates the second DAC segment 96 (DAC2 in FIG. 11A).

At step 164, the controller 102 determines how many of the currentelements 150 of the first DAC segment 94 (DAC1 in FIG. 11) are to beactivated in response to q (y=0 because there is no swapping),determines which of the elements to activate using DWA, and thenactivates these elements. For example, if q=0101, then the controller102 determines that five of the elements 150 are to be activated.

Next, the controller 102 uses DWA to determine which five of the currentelements 150 to activate, and activates these five current elements.

Then, at step 166, the first DAC segment 94 effectively multiplies byapproximately four the signal generated by the active elements 150 togenerate I_(analog) _(—) _(output) (because the second DAC segment 96 isinactive, the first DAC segment generates I_(analog) _(—) _(out) in itsentirety). As described above, this multiply by four is because theelements 150 each represent a bit in the 2²=4 bit position, and isinherently effected by the gains of the DAC elements 150 of the firstDAC segment 94 being approximately four times the gains of the DACelements 152 ₁ and 152 ₂, and twice the gains of the DAC elements 152 ₃and 152 ₄, of the second DAC segment 96.

During a second cycle position for r=0, at step 168 the controller 102activates the elements 152 ₁, and 152 ₂, and at a step 170 activates theelement 152 ₃, of the second DAC segment 96 (DAC2 in FIG. 11A) togenerate a second component of I_(analog-out)—as described above,however, the controller 102 deactivates the elements 152 ₁, 152 ₂, and152 ₃ if q=x=r=0.

At step 172, the second DAC segment 96 effectively multiplies byapproximately two the signal generated by the active element 152 ₃. Asdescribed above, this multiply by two is because the element 152 ₃represents a bit in the 2¹=2 bit position, and is inherently effected bythe gain of the DAC element 152 ₃ being approximately twice the gains ofeach of the DAC elements 152 ₁ and 152 ₂.

At step 174, the controller 102 sets y=1 because the active elements 152₁, 152 ₂, and 152 ₃ take the place of one of the current elements 150that the controller would otherwise activate in response to q.

Then, at step 176, the controller 102 determines how many of the currentelements 150 of the first DAC segment 94 (DAC1 in FIG. 11A) are to beactivated in response to q−1, determines which of the elements toactivate using DWA, and then activates these elements. For example, ifq=0101, then q−0001=0100 and the controller 102 determines that four ofthe current elements 150 are to be activated. Next, the controller 102uses DWA to determine which four of the current elements 150 toactivate, and activates these four current elements.

Then, at step 178, the first DAC segment 94 effectively multiplies byapproximately four the signal generated by the active elements 150 togenerate a first component of I_(analog) _(—) _(output). As describedabove, this multiply by four is because the elements 150 each representa bit in the 2² bit position, and is inherently effected by the gains ofthe DAC elements 150 of the first DAC segment 94 being approximatelytwice the gains of the DAC elements 152 ₃ and 152 ₄, and approximatelyfour times the gains of the DAC elements 152 ₁ and 152 ₂, of the secondDAC segment 96.

Next, at step 180, the first and second components of I_(analog) _(—)_(out) are summed at the summing node 100 to generate I_(analog) _(—)_(out).

During a third cycle position for r=0, at step 182 the controller 102activates the elements 152 ₁, and 152 ₂, and at a step 184 activates theelement 152 ₄, of the second DAC segment 96 (DAC2 in FIG. 11A) togenerate a second component of I_(analog) _(—) _(out)—as describedabove, however, the controller 102 deactivates the elements 152 ₁, 152₂, and 152 ₃ if q=x=r=0.

At step 186, the second DAC segment 96 effectively multiplies byapproximately two the signal generated by the active element 152 ₄. Asdescribed above, this multiply by two is because the element 152 ₄represents a bit in the 2¹ bit position, and is inherently effected bythe gain of the DAC elements 152 ₄ of the second DAC segment 96 beingapproximately twice the gains of each of the DAC elements 152 ₁ and 152₂ of the second DAC segment.

At step 188, the controller 102 sets y=1 because the active elements 152₁, 152 ₂, and 152 ₄ take the place of one of the current elements 150that the controller would otherwise activate in response to q.

Then, at step 189, the controller 102 determines how many of the currentelements 150 of the first DAC segment 94 (DAC1 in FIG. 11A) are to beactivated in response to q−1, determines which of the elements toactivate using DWA, and then activates these elements. For example, ifq=0101, then q−0001=0100 and the controller 102 determines that four ofthe current elements 150 are to be activated. Next, the controller 102uses DWA to determine which four of the elements 150 to activate, andactivates these four elements.

Next, at step 190, the first DAC segment 94 effectively multiplies byapproximately four the signal generated by the active elements 150 togenerate a first component of I_(analog) _(—) _(output). As describedabove, this multiply by four is because the elements 150 each representa bit in the 2² bit position, and is inherently effected by the gains ofthe DAC elements 150 of the first DAC segment 94 being approximatelytwice the gains of the DAC elements 152 ₃ and 152 ₄, and approximatelyfour times the gains of the DAC elements 152 ₁ and 152 ₂, of the secondDAC segment 96.

Then, at step 192, the first and second components of I_(analog) _(—)_(out) are summed at the summing node 100 to generate I_(analog) _(—)_(out).

And during a fourth cycle position for r=0, at step 194 the controller102 activates the elements 152 ₃ and 152 ₄ of the second DAC segment 96(DAC2 in FIG. 11) to generate a second component of I_(analog-out)—asdescribed above, however, the controller 102 deactivates the elements152 ₃ and 152 ₄ if q=x=r=0.

At step 196, the second DAC segment 96 effectively multiplies byapproximately two the signal generated by the active elements 152 ₃ and152 ₄. As described above, this multiply by two is because the elements152 ₃ and 152 ₄ each represent a bit in the 2¹ bit position, and isinherently effected by the gain of the DAC elements 152 ₃ and 152 ₄being approximately twice the gains of the DAC elements 152 ₁ and 152 ₂also of the second DAC segment 96.

At step 198, the controller 102 sets y=1 because the active elements 152₃ and 152 ₄ take the place of one of the current elements 150 that thecontroller would otherwise activate in response to q.

Then, at step 200, the controller 102 determines how many of the currentelements 150 of the first DAC segment 94 (DAC1 in FIG. 1) are to beactivated in response to q−1, determines which of the elements toactivate using DWA, and then activates these elements. For example, ifq=0101, then q−0001=0100 and the controller 102 determines that four ofthe elements 150 are to be activated. Next, the controller 102 uses DWAto determine which four of the elements 150 to activate, and activatesthese four elements.

Next, at step 202, the first DAC segment 94 effectively multiplies byapproximately four the signal generated by the active elements 150 togenerate a first component of I_(analog) _(—) _(output). As describedabove, this multiply by four is because the elements 150 each representa bit in the 2² bit position, and is inherently effected by the gains ofthe DAC elements 150 being approximately twice the gains of the DACelements 152 ₃ and 152 ₄, and approximately four times the gains of theDAC elements 152 ₁ and 152 ₂, of the second DAC segment 96.

Then, at step 204, the first and second components of I_(analog) _(—)_(out) are summed at the summing node 100 to generate I_(analog) _(—)_(out).

The controller 102 keeps track of the cycle positions for r, and repeatsthe above-described sequential, cyclic procedure for subsequentoccurrences of r=0.

Referring to FIG. 11B, during a first sequence, or cycle, position forr=1, at step 206 the controller 102 activates the element 152 ₁ of thesecond DAC segment 96 (DAC2 in FIG. 11B) to generate a second componentof I_(analog-out).

At step 208, the controller 102 determines how many of the currentelements 150 of the first DAC segment 94 (DAC1 in FIG. 11) are to beactivated in response to q (y=0 because no elements 152 are beingswapped for an element 150), determines which of the elements toactivate using DWA, and then activates these elements. For example, ifq=0101, then the controller 102 determines that five of the currentelements 150 are to be activated. Next, the controller 102 uses DWA todetermine which five of the current elements 150 to activate, andactivates these five current elements.

Then, at step 210, the first DAC segment 94 effectively multiplies byapproximately four the signal generated by the active elements 150 togenerate I_(analog) _(—) _(output). As described above, this multiply byfour is because the elements 150 each represent a bit in the 2² bitposition, and is inherently effected by the gains of the DAC elements150 of the first DAC segment 94 being approximately four times the gainsof the DAC elements 152 ₁ and 152 ₂, and twice the gains of the DACelements 152 ₃ and 152 ₄, of the second DAC segment 96.

Next, at step 212, the first and second components of I_(analog) _(—)_(out) are summed at the summing node 100 to generate I_(analog) _(—)_(out).

During a second cycle position for r=1, at step 214 the controller 102activates the element 152 ₂ of the second DAC segment 96 (DAC2 in FIG.11B) to generate a second component of I_(analog-out).

At step 216, the controller 102 determines how many of the currentelements 150 of the first DAC segment 94 (DAC1 in FIG. 11) are to beactivated in response to q (y=0 because no elements 152 are beingswapped for an element 150), determines which of the elements toactivate using DWA, and then activates these elements. For example, ifq=0101, then the controller 102 determines that five of the currentelements 150 are to be activated. Next, the controller 102 uses DWA todetermine which five of the current elements 150 to activate, andactivates these five current elements.

Then, at step 218, the first DAC segment 94 effectively multiplies byapproximately four the signal generated by the active elements 150 togenerate I_(analog) _(—) _(output). As described above, this multiply byfour is because the elements 150 each represent a bit in the 2² bitposition of x, and is inherently effected by the gains of the DACelements 150 of the first DAC segment 94 being approximately four timesthe gains of the DAC elements 152 ₁ and 152 ₂, and twice the gains ofthe DAC elements 152 ₃ and 152 ₄, of the second DAC segment 96.

Next, at step 220, the first and second components of I_(analog) _(—)_(out) are summed at the summing node 100 to generate I_(analog) _(—)_(out).

During a third cycle position for r=1, at step 222 the controller 102activates the element 152 ₁, and at a step 224 activates the elements152 ₃ and 152 ₄, of the second DAC segment 96 (DAC2 in FIG. 11B) togenerate a second component of I_(analog-out).

At step 226, the second DAC segment 96 effectively multiplies byapproximately two the signals generated by the active elements 152 ₃ and152 ₄. As described above, this multiply by two is because the elements152 ₃ and 152 ₄ each represent a bit in the 2¹ bit position, and isinherently effected by the gain of the DAC elements 152 ₃ and 152 ₄being approximately twice the gains of the DAC elements 152 ₁ and 152 ₂also of the second DAC segment.

At step 228, the controller 102 sets y=1 because the active elements 152₃ and 152 ₄ take the place of one of the current elements 150 that thecontroller would otherwise activate in response to q.

Then, at step 230, the controller 102 determines how many of the currentelements 150 of the first DAC segment 94 (DAC1 in FIG. 1) are to beactivated in response to q−1, determines which of the elements toactivate using DWA, and then activates these elements. For example, ifq=0101, then q−0001=0100 and the controller 102 determines that four ofthe current elements 150 are to be activated. Next, the controller 102uses DWA to determine which four of the current elements 150 toactivate, and activates these four current elements.

Next, at step 232, the first DAC segment 94 effectively multiplies byapproximately four the signal generated by the active elements 150 togenerate a first component of I_(analog) _(—) _(output). As describedabove, this multiply by four is because the elements 150 each representa bit in the 2² bit position, and is inherently effected by the gains ofthe DAC elements 150 of the first DAC segment 94 being approximatelytwice the gains of the DAC elements 152 ₃ and 152 ₄, and approximatelyfour times the gains of the DAC elements 152 ₁ and 152 ₂, of the secondDAC segment 96.

Next, at step 234, the first and second components of I_(analog) _(—)_(out) are summed at the summing node 100 to generate I_(analog) _(—)_(out).

And during a fourth cycle position for r=1, at step 236 the controller102 activates the element 152 ₂, and at a step 238 activates theelements 152 ₃ and 152 ₄, of the second DAC segment 96 (DAC2 in FIG.11B) to generate a second component of I_(analog-out).

At step 240, the second DAC segment 96 effectively multiplies byapproximately two the signals generated by the active elements 152 ₃ and152 ₄. As described above, this multiply by two is because the elements152 ₃ and 152 ₄ each represent a bit in the 2¹ bit position, and isinherently effected by the gain of the DAC elements 152 ₃ and 152 ₄being approximately twice the gains of the DAC elements 152 ₁ and 152 ₂also of the second DAC segment.

At step 242, the controller 102 subtracts sets y=1 because the activeelements 152 ₃ and 152 ₄ take the place of one of the current elements150 that the controller would otherwise activate in response to q.

Then, at step 244, the controller 102 determines how many of the currentelements 150 of the first DAC segment 94 (DAC1 in FIG. 1) are to beactivated in response to q−1, determines which of the elements toactivate using DWA, and then activates these elements. For example, ifq=0101, then q−0001=0100 and the controller 102 determines that four ofthe current elements 150 are to be activated. Next, the controller 102uses DWA to determine which four of the current elements 150 toactivate, and activates these four current elements.

Next, at step 246, the first DAC segment 94 effectively multiplies byapproximately four the signal generated by the active elements 150 togenerate a first component of I_(analog) _(—) _(output). As describedabove, this multiply by four is because the elements 150 each representa bit in the 2² bit position, and is inherently effected by the gains ofthe DAC elements 150 of the first DAC segment 94 being approximatelytwice the gains of the DAC elements 152 ₃ and 152 ₄, and approximatelyfour times the gains of the DAC elements 152 ₁ and 152 ₂, of the secondDAC segment 96.

Then, at step 248, the first and second components of I_(analog) _(—)_(out) are summed at the summing node 100 to generate I_(analog) _(—)_(out).

The controller 102 keeps track of the cycle positions for r, and repeatsthe above-described sequential, cyclic procedure of FIG. 11B forsubsequent occurrences of r=1.

Referring to FIG. 11C, during a first cycle position for r=2, at step250 the controller 102 activates the elements 152 ₁ and 152 ₂ of thesecond DAC segment 96 (DAC2 in FIG. 11C) to generate a second componentof I_(analog-out).

At step 252, the controller 102 determines how many of the currentelements 150 of the first DAC segment 94 (DAC1 in FIG. 11C) are to beactivated in response to q (y=0 because no elements 152 are swapped foran element 150), determines which of the elements to activate using DWA,and then activates these elements.

Then, at step 254, the first DAC segment 94 effectively multiplies byapproximately four the signal generated by the active elements 150 togenerate I_(analog) _(—) _(output).

Next, at step 256, the first and second components of I_(analog) _(—)_(out) are summed at the summing node 100 to generate I_(analog) _(—)_(out).

During a second cycle position for r=2, at step 258 the controller 102activates the element 152 ₃ of the second DAC segment 96 (DAC2 in FIG.11C).

At step 260, the second DAC segment 96 effectively multiplies byapproximately two the signal generated by the active element 152 ₃ togenerate a second component of I_(analog-out).

At step 262, the controller 102 determines how many of the currentelements 150 of the first DAC segment 94 (DAC1 in FIG. 11) are to beactivated in response to q (y=0 because no elements 152 are swapped foran element 150), determines which of the elements to activate using DWA,and then activates these elements.

Then, at step 264, the first DAC segment 94 effectively multiplies byapproximately four the signal generated by the active elements 150 togenerate I_(analog) _(—) _(output).

Next, at step 266, the first and second components of I_(analog) _(—)_(out) are summed at the summing node 100 to generate I_(analog) _(—)_(out).

During a third cycle position for r=2, at step 268 the controller 102activates the element 152 ₄ of the second DAC segment 96 (DAC2 in FIG.11C).

At step 270, the second DAC segment 96 effectively multiplies byapproximately two the signal generated by the active element 152 ₄ togenerate a second component of I_(analog-out).

At step 272, the controller 102 determines how many of the currentelements 150 of the first DAC segment 94 (DAC1 in FIG. 11) are to beactivated in response to q (y=0), determines which of the elements toactivate using DWA, and then activates these elements.

Then, at step 274, the first DAC segment 94 effectively multiplies byapproximately four the signal generated by the active elements 150 togenerate I_(analog) _(—) _(output).

Next, at step 276, the first and second components of I_(analog) _(—)_(out) are summed at the summing node 100 to generate I_(analog) _(—)_(out).

And during a fourth cycle position for r=2, at step 278 the controller102 activates the elements 152 ₁ and 152 ₂, and at a step 280 activatesthe elements 152 ₃ and 152 ₄, of the second DAC segment 96 (DAC2 in FIG.11C) to generate a second component of I_(analog-out).

At step 282, the second DAC segment 96 effectively multiplies byapproximately two the signals generated by the active elements 152 ₃ and152 ₄.

At step 284, the controller 102 sets y=1 because the active elements 152₃ and 152 ₄ take the place of one of the current elements 150 that thecontroller would otherwise activate in response to q.

Then, at step 286, the controller 102 determines how many of the currentelements 150 of the first DAC segment 94 (DAC1 in FIG. 11C) are to beactivated in response to q−1, determines which of the elements toactivate using DWA, and then activates these elements.

Next, at step 288, the first DAC segment 94 effectively multiplies byapproximately four the signal generated by the active elements 150 togenerate a first component of I_(analog) _(—) _(output).

Then, at step 290, the first and second components of I_(analog) _(—)_(out) are summed at the summing node 100 to generate I_(analog) _(—)_(out).

The controller 102 keeps track of the cycle positions for r, and repeatsthe above-described sequential, cyclic procedure of FIG. 11C forsubsequent occurrences of r=2.

Referring to FIG. 11D, during a first cycle position for r=3, at step292 the controller 102 activates the element 152 ₁, and at a step 294activates the element 152 ₃, of the second DAC segment 96 (DAC2 in FIG.11D) to generate a second component of I_(analog-out).

At step 296, the second DAC segment 96 effectively multiplies byapproximately two the signal generated by the active element 152 ₃.

At step 298, the controller 102 determines how many of the currentelements 150 of the first DAC segment 94 (DAC1 in FIG. 11D) are to beactivated in response to q (y=0), determines which of the elements toactivate using DWA, and then activates these elements.

Then, at step 300, the first DAC segment 94 effectively multiplies byapproximately four the signal generated by the active elements 150 togenerate I_(analog) _(—) _(output).

Next, at step 302, the first and second components of I_(analog) _(—)_(out) are summed at the summing node 100 to generate I_(analog) _(—)_(out).

During a second cycle position for r=3, at step 304 the controller 102activates the element 152 ₁, and at a step 306 activates the element 152₄, of the second DAC segment 96 (DAC2 in FIG. 11D) to generate a secondcomponent of I_(analog-out).

At step 308, the second DAC segment 96 effectively multiplies byapproximately two the signal generated by the active element 152 ₄.

At step 310, the controller 102 determines how many of the currentelements 150 of the first DAC segment 94 (DAC1 in FIG. 11D) are to beactivated in response to q (y=0), determines which of the elements toactivate using DWA, and then activates these elements.

Then, at step 312, the first DAC segment 94 effectively multiplies byapproximately four the signal generated by the active elements 150 togenerate I_(analog) _(—) _(output).

Next, at step 314, the first and second components of I_(analog) _(—)_(out) are summed at the summing node 100 to generate I_(analog) _(—)_(out).

During a third cycle position for r=3, at step 316 the controller 102activates the element 152 ₂, and at a step 318 activates the element 152₃, of the second DAC segment 96 (DAC2 in FIG. 11D) to generate a secondcomponent of I_(analog-out).

At step 320, the second DAC segment 96 effectively multiplies byapproximately two the signal generated by the active element 152 ₃.

At step 322, the controller 102 determines how many of the currentelements 150 of the first DAC segment 94 (DAC1 in FIG. 11) are to beactivated in response to q (y=0 because no elements 152 are swapped foran element 150), determines which of the elements to activate using DWA,and then activates these elements.

Then, at step 324, the first DAC segment 94 effectively multiplies byapproximately four the signal generated by the active elements 150 togenerate a first component of I_(analog) _(—) _(output).

Next, at step 326, the first and second components of I_(analog) _(—)_(out) are summed at the summing node 100 to generate I_(analog) _(—)_(out).

And during a fourth cycle position for r=3, at step 328 the controller102 activates the element 152 ₂, and at a step 330 activates the element152 ₄, of the second DAC segment 96 (DAC2 in FIG. 11D) to generate asecond component of I_(analog-out).

At step 332, the second DAC segment 96 effectively multiplies byapproximately two the signal generated by the active element 152 ₄.

At step 334, the controller 102 determines how many of the currentelements 150 of the first DAC segment 94 (DAC1 in FIG. 11) are to beactivated in response to q (y=0 because no elements 152 are beingswapped for an element 150), determines which of the elements toactivate using DWA, and then activates these elements.

Then, at step 336, the first DAC segment 94 effectively multiplies byapproximately four the signal generated by the active elements 150 togenerate a first component of I_(analog) _(—) _(output).

Next, at step 338, the first and second components of I_(analog) _(—)_(out) are summed at the summing node 100 to generate I_(analog) _(—)_(out).

The controller 102 keeps track of the cycle positions for r, and repeatsthe above-described sequential, cyclic procedure of FIG. 11D forsubsequent occurrences of r=3.

Still referring to FIGS. 7, 10, and 11, as described above, the firstDAC segment 94 of the 6-bit version of the segmented DAC 90 uses DWA toaverage/remove the non-linearity caused by its mismatch error byconverting the mismatch error to a constant gain error, at leastideally.

For the second DAC segment 96, the average mismatch error over asixteen-cycle grouping of the possible four events for each of r=0, r=1,r=2, and r=3, respectively, is a constant offset given by the followingequation:

$\begin{matrix}{\beta = \frac{e_{152\_ 1} + e_{152\_ 2} + e_{152\_ 3} + e_{152\_ 4}}{4}} & (8)\end{matrix}$where e₁₅₂ _(—) ₁=G₁₅₂ _(—) ₁−G is the quantization error of the element152 ₁, e₁₅₂ _(—) ₂=G₁₅₂ _(—) ₂−G is the quantization error of theelement 152 ₂, e₁₅₂ _(—) ₃=G₁₅₂ _(—) ₃−2G is the quantization error ofthe element 152 ₃, and e₁₅₂ _(—) ₄=G₁₅₂ _(—) ₄−2G is the quantizationerror of the element 152 ₄. Per equation (8), the mismatch error of thesecond DAC segment 96 is effectively converted into the constant offseterror β (as described above e₁₅₂ _(—) ₁, e₁₅₂ _(—) ₂, e₁₅₂ _(—) ₃, ande₁₅₂ _(—) ₄ can be positive or negative).

As described above, because the mismatch errors of the first and secondDAC segments 94 and 96 are, at least ideally, converted into a constantgain error and a constant offset error β, respectively, the mismatcherror introduced by component mismatch in the first and second DACsegments is effectively eliminated, and, therefore, adds no nonlinearitynoise that degrades the SNR of the 6-bit version of the segmented DAC90, or of a sigma-delta ADC that incorporates the segmented DAC.

But because the DAC elements 152 ₁, 152 ₂, 152 ₃, and 152 ₄ of thesecond DAC segment 96 are sometimes “swapped” into the first DAC segment94 as described above to obtain the constant offset β for the second DACsegment, the effective gain error of the first DAC segment is, inactuality, not constant, and, therefore, this non-constant gain errormay add some non-linearity noise that does degrade the SNR of the 6-bitversion of the segmented DAC 90. Specifically, the gain α of the firstDAC segment 94 is given by the following equation:

$\begin{matrix}{\alpha = {1 + \frac{e_{150\_ 1} + \ldots + e_{150\_ 15}}{den}}} & (9)\end{matrix}$where den (short for “denominator”) has a variation depending upon thesequence of input numbers from the quantizer 18 (FIG. 1) to the 6-bitversion of the segmented feedback DAC 90. For example, if the sequencefrom the quantizer 18 is of all similar numbers, say (4, 4, 4, . . . 4,or 7, 7, 7, . . . , 7, etc.) then den is given by the followingequation:

$\begin{matrix}{{den} = \left( {x*\frac{15}{{{quotient}\left( \frac{x}{4} \right)} - \left( \frac{3 - {{remainder}\left( \frac{x}{4} \right)}}{4} \right)}} \right)} & (10)\end{matrix}$where, for example, quotient (6/4)=1 and remainder (6/4)=2.

The range of a for any sequence of numbers from the quantizer 18(FIG. 1) is as follows:

$\begin{matrix}{\alpha = {{1 + {\frac{e_{150\_ 1} + \ldots + e_{150\_ 15}}{240}\mspace{14mu}{to}\mspace{14mu}\alpha}} = {1 + \frac{e_{150\_ 1} + \ldots + e_{150\_ 15}}{63}}}} & (11)\end{matrix}$

(i.e., 63≦den≦240, where den may take on a non-integer value within thisrange).

Furthermore, per equation (8), the offset error for the 6-bit version ofthe segmented DAC 90 is

${\beta = \frac{e_{150\_ 1} + e_{150\_ 2} + e_{150\_ 3} + e_{150\_ 4}}{2}},$which is constant for any sequence whatsoever; the offset β includesnonzero terms only from the mismatch errors of the elements of thesecond DAC segment 96.

If there is a sufficiently “busy” input signal to the sigma-delta ADC 10(FIG. 1), the output of the quantizer 18 (FIG. 1) varies significantlysuch as in the sequence (6, . . . , 58, 6, . . . , 58, . . . ). For sucha quantizer sequence, the gain α of the 6-bit version of the segmentedDAC 90, when used as the feedback DAC 22 of FIG. 1, is, or is close to:

$\begin{matrix}{\alpha = {1 + \frac{e_{150\_ 1} + \ldots + e_{150\_ 15}}{63}}} & (12)\end{matrix}$

That is, den is close to 63, which is at the lower end of the den rangeof expression (11), and approaches the gain of a 6-bit DWA DAC. Or,viewed another way, for a “busy” quantizer sequence, the gain error (therightmost term of the right side of equation (12)) of the 6-bit versionof the segmented DAC 90 approaches the constant gain error of a 6-bitnon-segmented DWA DAC.

If there is a mismatch error of no more than 1% (i.e., G₁₅₀ _(—)_(x)−4G≦±0.01·4G, G₁₅₂ _(—) _(x=3 or 4)−2G≦±0.01·2G, and G₁₅₂ _(—)_(x=1 or 2)−G≦±0.01·G) among the elements 150 and 152 of the first andsecond DAC segments 94 and 96, then the variation of the gain α, and,therefore, the variation in the linear distortion in the output of the6-bit version of the segmented DAC 90, will depend upon the sequence ofvalues input to the DAC. Extensive MATLAB simulations have shown thatfor a mismatch error of not more than 1%, the SNR of the ADC 10 (FIG.1), when incorporating the 6-bit version of the DAC 90 as the feedbackDAC 22, remains better than 108 dB. This implies that the variation inthe gain error (the right-most term on the right side of equation (9)above) is below −108 dB.

Furthermore, if the gain α of the 6-bit version of the DAC 90 variesbetween two values α₁ to α₂, then the noise introduced into the outputANALOG_OUT of the ADC 10 (FIG. 1) by the DAC 90 when used as thefeedback DAC is:

$\begin{matrix}{20*\log\; 10\left\{ \frac{\alpha_{1} - \alpha_{2}}{{oversampling}\mspace{14mu}{rate}} \right\}} & (13)\end{matrix}$

If the gain α varies between more than two values, then the expressionfor the introduced noise may be more complex, but the SNR of the ADC 10(FIG. 1) will still remain better than 108 dB when including the 6-bitversion of the segmented DAC 90 at an oversampling rate of at least 128.

Referring to FIGS. 7, 10, and 11, alternate embodiments of the 6-bitversion of the segmented DAC 90 are contemplated. For example, the DACcurrent elements 150 and 152 may be capacitor elements or other types ofDAC elements. Furthermore, the controller 102 may perform theabove-sequences of steps in different orders.

FIG. 12 is a diagram of an audio system 350, which includes thesegmented DAC 90 of FIG. 7, according to an embodiment.

The system 350 includes an antenna 352, input amplifier 354, inputdemodulator-filter 356, sigma-delta ADC 358, audio processor 360, outputDAC 362, output amplifier 364, audio renderer 366, and controller 368(the controller 368 may be separate from, include, or be part of thecontroller 102 (FIG. 7) of the DAC 90). The ADC 358 includes the DAC 90(FIG. 7) as a feedback DAC, and may otherwise be similar to the ADC 10of FIG. 1. Furthermore, the audio renderer 366 may be one or morespeakers.

In operation, the controller 368 controls the aforementioned componentsof the system 350 such that in an embodiment, the system operates asfollows.

The antenna 352 receives an analog signal, such as an AM or FM radiosignal, and the amplifier 354 amplifies the signal.

The demodulator-filter demodulates and conditions the amplified analogsignal.

The ADC converts the demodulated and conditioned analog signal into adigital signal, and the processor 360 processes the digital signal(e.g., enhances the quality of the signal, or adds audio effects to thesignal).

The DAC 362 converts the processed digital audio signal into an analogaudio signal, the amplifier 364 amplifiers the analog audio signal, andthe renderer 366 renders the amplified analog audio signal.

Still referring to FIG. 12, alternate embodiments of the system 350 arecontemplated. For example, the system 350 may be a type of system otherthan an audio system. Furthermore, although described as including oneDAC 90 in the ADC 358, the system 350 may include more than one DAC 90,or may include a DAC 90 that is not part of the ADC.

Even though various embodiments and advantages of the present disclosurehave been set forth in the foregoing description, the present disclosureis illustrative only, and changes may be made in detail and yet remainwithin the broad principles of the present disclosure. Moreover, thefunctions performed by various components described above can becombined to be performed by fewer elements, separated and performed bymore elements, or combined into different functional blocks dependingupon the nature of the electronic system to which the present disclosureis being applied, as will be appreciated by those skilled in the art. Atleast some of the components described above may be implemented usingeither digital or analog circuitry, or a combination of both, and also,where appropriate, may be realized through software executing onsuitable processing circuitry. It should also be noted that thefunctions performed by various components discussed above can becombined and performed by fewer elements or separated and performed byadditional elements depending on the nature of the DAC 90 of FIG. 7.

From the foregoing it will be appreciated that, although specificembodiments have been described herein for purposes of illustration,various modifications may be made without deviating from the spirit andscope of the disclosure. Furthermore, where an alternative is disclosedfor a particular embodiment, this alternative may also apply to otherembodiments even if not specifically stated.

What is claimed is:
 1. A digital-to-analog converter, comprising: afirst segment including a first number of first elements that areconfigured to generate a first analog signal in response to a firstportion of a digital signal; a second segment including a second numberof second elements that are configured to generate a second analogsignal in response to a second portion of the digital signal; a combinerconfigured to combine the first analog signal and the second analogsignal to generate a resulting analog signal; and a controllerconfigured to deactivate one of the first elements and to activate oneof the second elements in place of the deactivated one of the firstelements.
 2. The digital-to-analog converter of claim 1 wherein: thefirst portion of the digital signal includes a quotient of the digitalsignal divided by an integer; and the second portion of the digitalsignal includes a remainder of the digital signal divided by theinteger.
 3. The digital-to-analog converter of claim 1 wherein: thefirst portion of the digital signal includes a quotient of the digitalsignal divided by an integer power of base two; and the second portionof the digital signal includes a remainder of the digital signal dividedby the integer power of base two.
 4. The digital-to-analog converter ofclaim 1 wherein: the first portion of the digital signal has a firstrange of values; and the first number is one less than a number of thevalues in the first range.
 5. The digital-to-analog converter of claim 1wherein: the first portion of the digital signal has maximum value; andthe first number is equal to the maximum value.
 6. The digital-to-analogconverter of claim 1 wherein: the first portion of the digital signalincludes a most-significant portion of the digital signal; and thesecond portion of the digital signal includes a least-significantportion of the digital signal.
 7. The digital-to-analog converter ofclaim 1 wherein each of the first elements has approximately a samegain.
 8. The digital-to-analog converter of claim 1 wherein each of thesecond elements has approximately a same gain.
 9. The digital-to-analogconverter of claim 1 wherein: a first group of the second elements eachhas approximately a first gain; and a second group of the secondelements each has approximately a second gain that is different from thefirst gain.
 10. The digital-to-analog converter of claim 1 wherein: eachof the second elements has a respective gain; and each of the firstelements has approximately a gain that is approximately an integermultiple of the respective gain of each of the second elements.
 11. Thedigital-to-analog converter of claim 1 wherein the combiner includes asummer configured to generate the resulting analog signal equal to a sumof the first and second analog signals.
 12. The digital-to-analogconverter of claim 1 wherein: the first and second signals respectivelyinclude first and second analog currents; and the combiner includes anode that is configured to receive the first and second analog currentsand to provide the resulting current equal to a sum of the first andsecond analog currents.
 13. The digital-to-analog converter of claim 1wherein the controller is configured to change, periodically, acorrespondence between the first elements and the first portion of thedigital signal.
 14. The digital-to-analog converter of claim 1 wherein:the first portion of the digital signal include at least one digit; andthe controller is configured to cause each of the first elements togenerate a portion of the analog signal corresponding to the at leastone digit approximately a same number of times over a period of time.15. The digital-to-analog converter of claim 1 wherein: the firstportion of the digital signal include at least one digit; and thecontroller is configured to cause each of the first elements to generatea portion of the analog signal corresponding to the at least one digitapproximately a same average number of times.
 16. The digital-to-analogconverter of claim 1 wherein the controller is configured to deactivateone of the first elements and to activate one of the second elements inplace of the deactivated one of the first elements in response to thesecond portion of the digital signal.
 17. An analog-to-digitalconverter, comprising: an input node configured to receive an analoginput signal; an output node configured to provide a digital outputsignal; a first combiner configured to generate an analog combinedsignal in response to the analog input signal and an analog feedbacksignal; a first filter configured to generate a filtered analog signalin response to the analog combined signal; a quantizer configured toconvert the filtered analog signal into an intermediate digital signal;a second filter configured to generate the output digital signal inresponse to the intermediate digital signal; and a digital-to-analogconverter configured to converter the intermediate digital signal intothe analog feedback signal, the digital-to-analog converter including afirst segment including a first number of first elements that areconfigured to generate a first analog signal in response to a firstportion of the intermediate digital signal, a second segment including asecond number of second elements that are configured to generate asecond analog signal in response to a second portion of the intermediatedigital signal, a second combiner configured to generate the analogfeedback signal in response to the first analog signal and the secondanalog signal, and a controller configured to deactivate one of thefirst elements and to activate one of the second elements in place ofthe deactivated one of the first elements.
 18. The analog-to-digitalconverter of claim 17 wherein the first combiner is configured togenerate an analog combined signal by subtracting the analog feedbacksignal from the analog input signal.
 19. The analog-to-digital converterof claim 17, further comprising: a sample-and-hold circuit configured togenerate a sample of the analog input signal; and wherein the firstcombiner is configured to generate the analog combined signal inresponse to the sample of the analog input signal and then analogfeedback signal.
 20. A system, comprising: an analog-to-digitalconverter, including an input node configured to receive an analog inputsignal, an output node configured to provide a digital output signal, afirst combiner configured to generate an analog combined signal inresponse to the analog input signal and an analog feedback signal, afirst filter configured to generate a filtered analog signal in responseto the analog combined signal, a quantizer configured to convert thefiltered analog signal into an intermediate digital signal, a secondfilter configured to generate the output digital signal in response tothe intermediate digital signal, and a digital-to-analog converterconfigured to converter the intermediate digital signal into the analogfeedback signal, the digital-to-analog converter including a firstsegment including a first number of first elements that are configuredto generate a first analog signal in response to a first portion of theintermediate digital signal, a second segment including a second numberof second elements that are configured to generate a second analogsignal in response to a second portion of the intermediate digitalsignal, a second combiner configured to generate the analog feedbacksignal in response to the first analog signal and the second analogsignal, and a controller configured to deactivate one of the firstelements and to activate one of the second elements in place of thedeactivated one of the first elements; and a control circuit coupled tothe analog-to-digital converter.
 21. The system of claim 20 wherein theanalog-to-digital converter includes a sigma-delta analog-to-digitalconverter.
 22. The system of claim 20 wherein the controller is part ofthe control circuit.
 23. A digital-to-analog converter, comprising: afirst segment including a first number of first elements that areconfigured to generate a first analog signal in response to a firstportion of a digital signal; a second segment including a second numberof second elements that are configured to generate a second analogsignal in response to a second portion of the digital signal; a combinerconfigured to combine the first analog signal and the second analogsignal to generate a resulting analog signal; and a controllerconfigured to match, dynamically, the first elements.
 24. Thedigital-to-analog converter of claim 23 wherein the controller isconfigured to match, dynamically, the first elements by data-weightaveraging the first elements.
 25. The digital-to-analog converter ofclaim 23 wherein the controller is configured to match, dynamically, thefirst elements by periodically changing a correspondence between thefirst elements and the first portion of the digital signal.
 26. Thedigital-to-analog converter of claim 23 wherein the controller isconfigured to match, dynamically, the first elements by changing acorrespondence between the first elements and the first portion of thedigital signal in response to the first portion of the digital signal.27. The digital-to-analog converter of claim 23 wherein: the firstportion of the digital signal includes at least one digit; and thecontroller is configured to match, dynamically, the first elements bycausing each of the first elements to generate a portion of the analogsignal corresponding to the at least one digit approximately a samenumber of times over a period of time.
 28. The digital-to-analogconverter of claim 23 wherein: the first portion of the digital signalinclude at least one digit; and the controller is configured to match,dynamically, the first elements by causing each of the first elements togenerate a portion of the analog signal corresponding to the at leastone digit approximately a same average number of times.
 29. Ananalog-to-digital converter, comprising: an input node configured toreceive an analog input signal; an output node configured to provide adigital output signal; a first combiner configured to generate an analogcombined signal in response to the analog input signal and an analogfeedback signal; a first filter configured to generate a filtered analogsignal in response to the analog combined signal; a quantizer configuredto convert the filtered analog signal into an intermediate digitalsignal; a second filter configured to generate the output digital signalin response to the intermediate digital signal; and a digital-to-analogconverter configured to converter the intermediate digital signal intothe analog feedback signal, the digital-to-analog converter including afirst segment including a first number of first elements that areconfigured to generate a first analog signal in response to a firstportion of the intermediate digital signal, a second segment including asecond number of second elements that are configured to generate asecond analog signal in response to a second portion of the intermediatedigital signal, a combiner configured to combine the first analog signaland the second analog signal to generate the feedback analog signal, anda controller configured to match, dynamically, the first elements.
 30. Asystem, comprising: an analog-to-digital converter, including an inputnode configured to receive an analog input signal; an output nodeconfigured to provide a digital output signal; a first combinerconfigured to generate an analog combined signal in response to theanalog input signal and an analog feedback signal; a first filterconfigured to generate a filtered analog signal in response to theanalog combined signal; a quantizer configured to convert the filteredanalog signal into an intermediate digital signal; a second filterconfigured to generate the output digital signal in response to theintermediate digital signal; and a digital-to-analog converterconfigured to converter the intermediate digital signal into the analogfeedback signal, the digital-to-analog converter including a firstsegment including a first number of first elements that are configuredto generate a first analog signal in response to a first portion of theintermediate digital signal, a second segment including a second numberof second elements that are configured to generate a second analogsignal in response to a second portion of the intermediate digitalsignal, a combiner configured to combine the first analog signal and thesecond analog signal to generate the feedback analog signal, and acontroller configured to match, dynamically, the first elements; and acontrol circuit coupled to the analog-to-digital converter.
 31. Thesystem of claim 30 wherein the analog-to-digital converter includes asigma-delta analog-to-digital converter.
 32. The system of claim 30wherein the controller is part of the control circuit.
 33. A method,comprising: generating a first analog signal with a firstdigital-to-analog converter in response to a first portion and a secondportion of a digital signal; generating a second analog signal with asecond digital-to-analog converter in response to the second portion ofthe digital signal; and combining the first and second analog signals togenerate an output analog signal.
 34. The method of claim 33 whereingenerating the first analog signal includes deactivating a portion ofthe first digital-to-analog converter in response to the second portionof the digital signal.
 35. The method of claim 33 wherein generating thefirst analog signal includes activating a portion of the firstdigital-to-analog converter in response to the second portion of thedigital signal.
 36. The method of claim 33 wherein generating the secondanalog signal includes generating the second analog signal in responseto the first portion of the digital signal.
 37. The method of claim 33wherein: generating the first analog signal includes deactivating aportion of the first digital-to-analog converter a first number of timesout of each second number of times that the second portion of thedigital signal has a value; and generating the second analog signalincludes activating a portion of the second digital-to-analog converterthe first number of times out of each second number of times that thesecond portion of the digital signal has the value.
 38. The method ofclaim 37 wherein the first number is one and the second number is two.39. The method of claim 37 wherein the first number is three and thesecond number is four.
 40. The method of claim 37 wherein the firstnumber is two and the second number is four.
 41. The method of claim 37wherein the first number is one and the second number is four.
 42. Themethod of claim 37 wherein the first number is zero and the secondnumber is four.
 43. A method, comprising: activating each of firstdigital-to-analog-converter elements approximately a same average numberof times in response to a first portion of a digital signal to generatea first analog signal; activating second digital-to-analog-converterelements in response to a second portion of the digital signal togenerate a second analog signal; combining the first analog signal andthe second analog signal to generate a resulting analog signal.
 44. Themethod of claim 43, further comprising activating the firstdigital-to-analog-converter elements in response to the second portionof the digital signal.